TSMC reportedly plots ultra-advanced sub-1 nm chips with 'trial' production starting in 2029
https://www.pcgamer.com/hardware/tsmc-reportedly-plots-ultra-advanced-sub-1-nm-chips-with-trial-production-starting-in-2029/
60 points · 28 comments · view on lemmy.world
28 Comments
homes@piefed.world · 21 pts · 137d
It’s ok to say ‘picometer’
eksb@programming.dev · 23 pts · 137d
The "Xnm" sizes have not related to any actual length for decades. It is purely marketing.
homes@piefed.world · 7 pts · 137d
lol, no kidding.
Do you have any more information on this? I’d like to know how the hell this happened.
eleijeep@piefed.social · 23 pts · 137d
It started out as gate-length and then when we started building 3D transistors with FinFETs and gate-all-around, where the 2-dimensional gate-length is not comparable to "flat" transistors, they had to instead estimate the effective equivalent 2D gate-length that would give the same transistor density.
So the process name is now no longer a measure of any tangible feature size but more a descriptor of transistor density that is loosely consistent with the prior convention.
homes@piefed.world · 6 pts · 137d
yes, I see now why you just said, "marketing"
lol
still, quite interesting
eleijeep@piefed.social · 6 pts · 137d
I wasn't the original commenter but I suppose you could call it marketing, sure.
Zetta@mander.xyz · 4 pts · 136d
appreciate the explanation good to see that it isn't actually purely marketing, in my opinion, and they try to keep the old meaning coherent with these more advanced generations
rem26_art@fedia.io · 2 pts · 137d
It seems like 1994 was where process nodes started to not be so correlated with their actual size, according to this IEEE article. In 1994, transistor features were actually smaller than what was advertised, up until the early 2000's, where the naming became smaller than physical size. From what I understand, most of the gains in computing power have come from other improvements in processes and transistor geometry.
I guess the industry never really bothered changing their naming schemes, or couldn't figure out a better way?
eleijeep@piefed.social · 7 pts · 137d
They actually decided to use Angstroms for the initial sub-nanometre processes.
FTA:
And Intel talked about it in 2021:
https://arstechnica.com/gadgets/2021/07/intels-foundry-roadmap-lays-out-the-post-nanometer-angstrom-era/
homes@piefed.world · 3 pts · 137d
well, there ya go
SaveTheTuaHawk@lemmy.ca · 1 pts · 137d
Angstrom is not the next unit down from nanometers.
Picometers are the next unit down. Angstrom is a non SI antiquated measure.
eleijeep@piefed.social · 1 pts · 137d
Yeah, it's pcgamer writing about silicon manufacturing. Even the headline is insane ("1nm chips" instead of "1nm process").
sik0fewl@piefed.ca · 1 pts · 136d
Sub-1000 pm, then.
Markuso213@piefed.social · 9 pts · 137d
This is very small.
homes@piefed.world · 1 pts · 137d
Yet big news!
eleijeep@piefed.social · 1 pts · 137d
You could fit about 7x10^16^ 1nm chips on one 30cm wafer.
Imagine a beowulf cluster of those!
PabloSexcrowbar@piefed.social · 1 pts · 137d
Source?
Asafum@lemmy.world · 7 pts · 137d
:P
PabloSexcrowbar@piefed.social · 2 pts · 137d
I dunno, I don't see any nanometers on there...
riskable@programming.dev · 1 pts · 136d
The flaws are immeasurable?
SaveTheTuaHawk@lemmy.ca · 1 pts · 136d
Walter Reed uses picometers to measure the POTUS' dick.
PabloSexcrowbar@piefed.social · 1 pts · 136d
Yes, but unlike the president's dick, I expect these transistors to do something productive.
just_an_average_joe@lemmy.dbzer0.com · -1 pts · 136d
What's the point? Its just stupid numbers. GPU's will get more and more expensive to justify these tech "advances".
We have known how to make these GPU's, the problem isn't how to make them smaller and smaller but how do we make more of them.
Gamers can't buy it to play, 3d artists can't buy it for rendering, even AI enthusiasts can't buy it to run local models. These news just feel like these people are living in their own bubble.
piccolo@sh.itjust.works · 3 pts · 136d
Increasing the transistors count means datacenters can use less gpus to do the same amount of work.
just_an_average_joe@lemmy.dbzer0.com · 1 pts · 136d
Don't these new GPU's need to be bought by the datacenters? Where do you think they will push to cost to? Can one 5090 do more than 2x 3090? It sure as hell going to cost twice as much.
You have to think how much faster this new chip is, and whether it is fast enough to justify the cost. Gone are the days of moore's law when transistors could double every 2 years.
We need more production capacity to bring down cost, not a slightly faster gpu
piccolo@sh.itjust.works · 2 pts · 136d
Smaller transistors means more processors per silicon wafer... litterally increasing production and driving cost down.
Zetta@mander.xyz · 2 pts · 136d
Technology advancements like this are going to keep on marching along no matter the price of the end good. There is massive demand for better and better silicone and that doesn't look like it's going to change pretty much ever, at least not in our lifetimes.
Also, every time you see these companies announcing new chips with smaller transistors, that means they built an entire new fab to produce these chips. The old fabs generally still stay operating if there is demand, so this does in fact increase capacity overall
just_an_average_joe@lemmy.dbzer0.com · 1 pts · 136d
There are limits tho, there's a general trend of diminishing returns. Moore's law is no longer applicable.
My point is that we want more innovation is production capacity, these new innovations are mostly for making money. What the company wants is to say "look at our new shiny thing its 10% better than previous gen but it will cost you 50% more than last gen, also last gen is deprecated".
All of this is motivated by the drive to make more money for the producers, not to help the enduser.